IP-Cores under the SignOnce IP License

AES IP-Cores for Encryption/Decryption and Key Expansion. These cores implement the AES (Advanced Encryption Standard, Rijndael) encryption standard, as described in the NIST (National Institute of Standards and Technology) Federal Information processing Standard (FIPS) Publication 197 document. The cores cover both encryption/decryption functions and key expansion, supporting any or all of the proposed key sizes (128/192/256-bit).

Xilinx FPGA Prototyping Boards

	Prototyping Board for Xilinx Virtex-II FPGAs in the FF896 (XC2V1000 to XC2V2000) and FF1152 (XC2V3000 to XC2V8000) package.
	Board modules for Xilinx Virtex/Virtex-E/Spartan-II FPGAs in the HQ-240 package.
	Board module EVALXCS-PQ208 for Xilinx Spartan FPGA XCS40/30/20 (5V) or XCS40XL/30XL/20XL (3.3V).

Power Modules

	Power Module PWR3 to easily generate the various supply voltages needed by the board modules with Virtex/Virtex-E/Spartan-II FPGAs.
	Power Module PWR3-L to easily generate the various supply voltages needed by the board modules with Virtex/Virtex-E/Spartan-II FPGAs.

Obsolete Products

Board module EVALXCV-HQ240 for Xilinx Virtex FPGAs in HQ-240 package. This product has been replaced with the board module for Xilinx Virtex/Virtex-E/Spartan-II FPGAs in the HQ-240 package.

Further Information

Data Sheets (Software)

• 173 KB AES IP-Cores for Encryption/Decryption and Key Expansion

User Manuals

• 563 KB Virtex-II prototyping board user manual
• 310 KB Virtex, Virtex-E or Spartan-II FPGA board user manual
• 118 KB PWR3 Power module user manual
•    65 KB PWR3-L Power module user manual
• 213 KB Spartan board user manual

Articles

• 169KB Xcell Article: Stackable Development Boards for Spartan-II, Virtex, and Virtex-E FPGAs
• Xcell Journal Online, Xcell 47: For Complex Designs, More is Better

Terms and Conditions

• 17KB Terms and Conditions