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Board Module EVALXC2S/XCV/XCVE-HQ240 for Xilinx FPGA Families Spartan-II, Virtex or Virtex-E
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As the successors of our
Virtex-based board we designed a
new set of boards with either a Spartan-II, Virtex or Virtex-E FPGA as
their cores. Like their predecessor, the new boards provide all the
necessary basic components needed in most of FPGA-based designs. We
additionally incorporated an optional large ZBT RAM onto the boards to
satisfy the needs of modern telecommunication and imaging
applications. All I/Os are routed to header connectors where you
connect your special purpose interfaces. By stacking several boards
you can easily cope with the complexity of a design which exceeds the
scope of a single FPGA. The boards are mechanically fully compatible
with their predecessor such that you can stack them together and reuse
the power module PWR3
as the supply for the various required supply and reference voltages.
Figure 1: Top view of the board module
Figure 2: Bottom view of the board module
- Download: Master Serial Mode (SPROM with socket), Slave Serial
Mode (XChecker header connector), Boundary Scan Mode (JTAG header
connector), SelectMAP Mode (header connector)
- Configuration from onboard SCPs: ISP SCPs programmable via JTAG,
sockets for OTP SCPs
- I/O bank reference voltages: Two adjustable
VREFs for 8 I/O banks (selectable via jumpers) or eight external
voltages (e.g. from power module
PWR3)
- Optional ZBT RAM
- Two separate crystal oscillators with sockets (DIL8 or DIL14)
- Jumpers to select between internal and external clock sources
- Four SMB connectors next to the FPGA for feeding high frequency
clocks
- Two header connectors (two rows with 50 pins each) for I/Os, clocks and
control signals
- Two header connectors (one row with 50 pins each)
for supply and reference voltages from power module
- Six ground clips
- Voltage supervisor with reset button
- Two additional user buttons
- Eight position DIP switch
- Display with eight LEDs
- "Done" LED
- Power LEDs
- Mode jumpers M0 / M1 / M2
- Daisy chain configuration with other board modules possible
- Several boards may be connected to form a stack
- Board size 100mm x 150mm
Applications
- ASIC Emulation
- Error monitoring and analysis
- Digital PLL circuits
- PWM controller
- Adaptive digital filters
- Signal multiplexers
- Stimuli generators
- High speed encoder/decoder
- Memory controller
- Interface controller
The board is also very well suited to:
- Evaluate the larger members
of the Spartan-II, Virtex / Virtex-E FPGA families in the PQ-208 or
HQ-240 packages, respectively.
- Experiment with different low voltage I/O standards.
- Implement custom designs utilizing the full power of
Virtex architecture.
- Test algorithms under real time conditions and watch the signals
with a logic analyzer.
- Quickly and easily expand the complexity of the system by stacking
several boards.
The board module EVALXC2S/XCV/XCVE is
equipped with a member of the Xilinx Spartan-II, Virtex or Virtex-E
FPGA family in the PQ208 or HQ-240 package, respectively. This board
is especially suited to test digital circuits during the early stages
of their development. You can easily attach a logic analyzer an watch
the signals in real time. The high count of system gates enables you
to implement circuits which reach the complexity of ASICs. The
configuration data of the FPGA is downloadable using one of four modes
(master serial mode (XChecker), slave serial mode (SPROM), boundary
scan mode (JTAG) and SelectMAP mode). The block diagram of Figure 3
shows the functional blocks of the board.
Figure 3: Block diagram of the board module
All general I/Os of the FPGA are routed to header connectors. If you
use I/O standards which need reference voltages, you can select up to
eight different voltage levels for all eight banks individually with
jumpers.
An optional ZBT RAM helps you to support memory demanding
implementations like imaging and telecommunication applications. The
clock input of this RAM is connected to the global clock GCK2 of the
FPGA to achieve a real synchronous system clock. Alternatively, you
can generate the RAM clock internally to the FPGA. In this case the
clock is gated through an output pin connected to the RAM clock input
via a jumper. The GCK2 clock may then not be driven externally.
By stacking several boards, you may implement circuits whose
complexity is beyond the scope of a single FPGA. The whole stack is
configurable with a single download by means of an external daisy
chain. You can also link the stacked boards in a JTAG chain.
Two sockets are provided to hold Xilinx OTP SCPs (two XC1704L in a
PLCC44 package). In addition, two ISP SCPs (XC1800 family) are mounted
on the back side of the board. You can program these SCPs using the
JTAG mode.
Four clock sources can be used where two of them are either an onboard
crystal oscillator or an external source. The other two sources are
always external sources. The crystal oscillators are mounted in
sockets and can therefore be exchanged easily. Both, a DIL-8 and a
DIL-14 package can be used. There is the possibility to terminate all
clock traces near the FPGA with resistors to ground. These resistors
may be mounted by you on the bottom side of the PCB.
A voltage supervisor circuit generates a short pulse of ca. 2ms
duration whenever the core supply voltage (VCCINT) drops below 2.2V
(1.7V for Virtex-E) and on power up. The polarity of the reset pulse
can be chosen to be either active high or active low. Such a reset
pulse is also generated when you press the reset button.
An eight position DIP switch is available for user specific
applications. In addition, there are three push buttons. One of them
is intended primarily for use as a reset button and is connected to
the voltage supervisor circuit. The other two buttons are available
for arbitrary purposes.
A row with eight LEDs may function as a display for status and error
messages. You may disconnect these LEDs from the I/O signals by means
of jumpers. This is especially useful if you stack several boards and
do not want to have the LEDs connected in parallel.
Due to the large number of different FPGA device types we only have
the most popular ones in stock. If you need a certain device type,
please ask for a quote.
You can find more detailed information in the user manuals:
There also exists an overview article that was published in the
Xcell 38 - Fourth Quarter 2000 edition of the Xilinx journal:
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